1. Field of the Invention
This invention relates to an output impedance matching network for a MIC (Microwave Integrated Circuit) power amplifier module used in solid state power amplifiers (SSPAs).
2. Description of the Related Art
A MIC power amplifier module has an output impedance matching network to match the power transistor output impedance to the load impedance. For example, an FET power transistor has an output impedance of several ohms, whereas the load may have an impedance of 50 .OMEGA.. Tuning an impedance matching network is important in space applications because it cuts down power loss, thus saving money and weight.
An example is a 20 W internally matched power amplifier Fujitsu model FLM1415L-20, used in space satellite applications at 1500 MHz. FIG. 1 shows a plan view of this microwave integrated circuit MIC SSPA, with the lid removed. A microwave signal is fed through an input microstrip transmission line 10 which is coupled via a ceramic feed-through 12 into a copper package 14, which is gold plated on the inside. The input transmission line is then coupled by twelve gold bond wires 16 to a microstrip power splitter 20 printed on an alumina substrate 22. Twelve bond wires are sufficient to handle the power provided by input transmission line 10. Alumina dielectric substrate 22 is bonded to the inside of copper package 14 by gold germanium or gold tin solder.
Two pairs of gold bond wires 26,28 allow sufficient power to be carried from the power splitter 20 to capacitors 30,32, respectively. The plates of one side of these capacitors are formed by printing gold metalizations 34,36 on barium tetratitinate high dielectric ceramic substrates 38,40, respectively. These substrates are soldered with gold germanium or gold tin solder to the inside of copper package 14, which forms the other plate of the capacitors. Metalizations 34,36 also serve as bond pads. A gallium arsenide field effect transistor (GaAsFET) Q1 has two connected sections Q1a and Q1b with a common gate connected by gold lead 42. The Q1a and Q1b common gate has gold bond pads 44,46, respectively. Q1a and Q1b are soldered to the inside of copper package 14 by gold tin solder. Eight gold bond wires 48a-48d and 50a-50d connect bond pads 34,36 of capacitors 30 and 32 to gold bond pads 44,46 of the common gate of Q1a and Q1b. Bond wires 48a-48d and 50a-50d provide an inductance which, together with capacitors 30 and 32, forms a low pass filter (e.g. an input impedance matching network) to match the impedance of 50 .OMEGA. from the input transmission line to a low impedance at the gate of Q1. Bond wires 48a-48d and 50a-50d are pre-tuned to the correct inductance by a machine which establishes the correct spacing and shape of each bond wire loop.
FIGS. 2 and 3 show progressively larger views of Q1a and Q1b and the attached bond wires. In addition to having a common gate with bond pads 44,46, Q1a and Q1b also have a common drain with gold bond pads 58,60, which are connected by lead 56. The FET source terminals utilize via holes to make contact from the source terminal metalization 59,61 on the top surface of the FET to ground, which is provided by the floor of the package H.
Q1 drain bond pads 58,60 are connected by two sets of eight gold bond wires 62a-62p to an output power combiner bonding pad 64; multiple wires are used to accommodate the input signal plus the DC bias current in the drain. The 16 gold bond wires form a series inductor. Biasing for Q1 (not shown) is done externally. Output power combiner 64 is a gold transmission line that is printed on an alumina dielectric substrate 66 and has a defined capacitance. Substrate 66 is soldered to the inside of copper package 14 by gold tin or gold germanium solder.
The combination of the output power combiner 64 capacitance and the inductance of the bond wires 62a-62p forms a low pass output impedance matching network between the Q1 drain, which has a low impedance of about 2 .OMEGA., and an output transmission line 68 which is connected to the opposite side of power combiner 64 and typically has a 50 .OMEGA. impedance.
The series inductance of bond wires 62a-62p is the most critical element of the impedance matching network, with the length, shape and proximity of the bond wires determining the series inductance. Slight changes in these parameters have a significant impact on both the device's output power and its power added efficiency (PAE), which is defined as (Power out RF--Power in RF) divided by (Power DC). Therefore, it is desirable to optimize the value of the series inductor by tailoring the size, shape and proximity of the bond wires for each internally matched power FET.
However, standard MIC assembly procedures typically preclude altering or replacing bond wires attached to the FET devices in high reliability applications, such as satellites. A key reliability concern is the integrity of the bond wires used in the FET. The reason for this is that if a technician physically moves a bond wire with a probe, the bond wire may pull the gold bond pad metalization off the FET drain substrate. The biggest problem is that a bond wire cannot be reattached to a damaged bond pad on Q1 and the power amplifier module must be scrapped.
One conventional way of dealing with the problem is to minimize the amount of physical movement of bond wires by a technician. This reduces breakage but requires that an additional stage having tunable capacitance and inductance be added to the circuit. This is undesirable because a two stage output creates losses and reduces the power added efficiency (PAE) . What would be more desirable would be to have only one stage of tuning for the output impedance matching network, and yet overcome the problem of the bond wires pulling bond pad metalization off the drain of Q1.
FIG. 4 is the electrical schematic for the SSPA of FIG. 1, showing the impedances that are involved in the output impedance matching network. The input transmission line 10 provides a signal to the input power splitter 22' shown in FIG. 1. All other electrical equivalents are indicated in a similar fashion. A pair of inductances 26' and 28' represent the inductances of bond wires 26 and 28. These are very short bond wires and have small inductances which are of little consequence in the circuit. Capacitances 30',32' correspond to capacitors 30, 32 and inductances 48'a-d,50'a-d represent the inductance of bond wires 48a-d,50a-d. As described in connection with FIG. 1, capacitances 30', 32' and inductances 48'a-d,50'a-d form an LC circuit, identified in FIG. 4 as input impedance matching network 52, to match the 50 .OMEGA. impedance of the input transmission line 10 to the low impedance of the Q1 gate.
The bond wire inductances 62'a-p are the primary components in the LC matching circuit, identified in FIG. 4 as the output impedence matching network 69, between the low (2 .OMEGA.) output impedance of the Q1 drain and the 50 .OMEGA. impedance of the output transmission line 68. Capacitance 64' of the output power combiner 64 is also included in the output impedance matching network. The output power combiner 64 utilizes eighth-wave length transmission lines, represented schematically by capacitors 64', which are coupled to the output transmission line 68.